View 89HPES3T3ZABC_4333684.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3-Lane 3-Port PCI Express(R) Switch
(R)
89HPES3T3 Data Sheet
Advance Information*
Device Overview
The 89HPES3T3 is a member of IDT's PRECISETM family of PCI Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports.
Features
High Performance PCI Express Switch - Three 2.5Gbps PCI Express lanes - Three switch ports - x1 Upstream port - Two x1 Downstream ports - Low latency cut-through switch architecture - Support for Max payload sizes up to 256 bytes - One virtual channel - Eight traffic classes - PCI Express Base Specification Revision 1.1 compliant Flexible Architecture with Numerous Configuration Options - Automatic lane reversal on all ports - Automatic polarity inversion on all lanes - Ability to load device configuration from serial EEPROM Legacy Support - PCI compatible INTx emulation - Bus locking
Highly Integrated Solution - Requires no external components - Incorporates on-chip internal memory for packet buffering and queueing - Integrates three 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features - Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) - Supports ECRC and Advanced Error Reporting - Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O - Compatible with Hot-Plug I/O expanders used on PC motherboards Power Management - Utilizes advanced low-power design techniques to achieve low typical power consumption - Supports PCI Power Management Interface specification (PCIPM 1.2) - Unused SerDes are disabled. - Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state Testability and Debug Features - Built in Pseudo-Random Bit Stream (PRBS) generator - Numerous SerDes test modes - Ability to bypass link training and force any link into any mode - Provides statistics and performance counters
Block Diagram
3-Port Switch Core / 3 PCI Express Lanes
Frame Buffer Route Table Port Arbitration Scheduler
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Mux / Demux
Phy Logical Layer
Mux / Demux
Phy Logical Layer
Mux / Demux
Phy Logical Layer
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
Figure 1 Internal Block Diagram
(Port 3)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 23
(c) 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
Five General Purpose Input/Output Pins - Each pin may be individually configured as an input or output - Each pin may be individually configured as an interrupt input - Four pins have selectable alternate functions Packaged in a 13mm x 13mm 144-ball BGA with 1mm ball spacing
Product Description Utilizing standard PCI Express interconnect, the PES3T3 provides the most efficient fan-out solution for applications requiring x1 connectivity, low latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.1. The PES3T3 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES3T3 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity.
Processor
Processor
North Bridge
Memory Memory Memory Memory
South Bridge
x1
PES3T3
x1
GE LOM
x1
1394
Figure 2 I/O Expansion Application
SMBus Interface The PES3T3 contains an SMBus master interface. This master interface allows the default configuration register values of the PES3T3 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin. Hot-Plug Interface The PES3T3 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES3T3 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES3T3 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES3T3. In response to an I/O expander interrupt, the PES3T3 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
2 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
General Purpose Input/Output The PES3T3 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control, and each GPIO pin is shared with another on-chip function. These alternate functions may be enabled via software or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES3T3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal PE0RP[0] PE0RN[0] PE0TP[0] PE0TN[0] PE2RP[0] PE2RN[0] PE2TP[0] PE2TN[0] PE3RP[0] PE3RN[0] PE3TP[0] PE3TN[0] PEREFCLKP PEREFCLKN
Type I O I O I O I
Name/Description PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for port 0. PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for port 0.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pair for port 2. PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for port 3. PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pair for port 3. PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is 100 MHz. Table 1 PCI Express Interface Pins
Signal MSMBCLK MSMBDAT
Type I/O I/O
Name/Description Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Table 2 SMBus Interface Pins
3 of 23
September 7, 2007
Advance Information
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pair for port 2.
IDT 89HPES3T3 Data Sheet
Signal GPIO[0]
Type I/O
Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 Table 3 General Purpose I/O Pins
GPIO[1] GPIO[2]
I/O I/O
GPIO[7]
I/O
GPIO[9]
I/O
Signal APWRDISN CCLKDS
Type I I
Name/Description Auxiliary Power Disable Input. When this pin is active, it disables the device from using auxiliary power supply. Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be override by modifying the SCLK bit in the downstream port's PCIELSTS register. Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the PA_PCIELSTS register. Fundamental Reset. Assertion of this signal resets all logic inside the PES3T3 and initiates a PCI Express fundamental reset. Table 4 System Pins (Part 1 of 2)
CCLKUS
I
PERSTN
I
4 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet Signal RSTHALT Type I Name/Description Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES3T3 executes the reset procedure and remains in a reset state with the Master SMBus active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by the SMBus master. Switch Mode. These configuration pins determine the PES3T3 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved Wake Input/Output. The WAKEN signal is an input or output. The WAKEN signal input/output selection can be made through WAKEDIR bit setting in the WAKEUPCNTL register. Table 4 System Pins (Part 2 of 2)
SWMODE[2:0]
I
WAKEN
I/O
Signal JTAG_TCK
Type I
Name/Description JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 5 Test Pins
JTAG_TDI JTAG_TDO
I O
JTAG_TMS JTAG_TRST_N
I I
Signal VDDCORE VDDI/O VDDPE VDDAPE VTTPE VSS
Type I I I I I I
Name/Description Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. PCI Express Termination Power. Ground. Table 6 Power and Ground Pins
5 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
Pin Characteristics
Note: Some input pads of the PES3T3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.
Function PCI Express Interface
Pin Name PE0RN[0] PE0RP[0] PE0TN[0] PE0TP[0] PE2RN[0] PE2RP[0] PE2TN[0] PE2TP[0] PE3RN[0] PE3RP[0] PE3TN[0] PE3TP[0] PEREFCLKN PEREFCLKP
Type I I O O I I O O I I O O I I I/O I/O I/O I I I I I I I/O I I O I I
Buffer CML
I/O Type Serial Link
Internal Resistor
Notes
LVPECL/ CML LVTTL LVTTL LVTTL
Diff. Clock Input STI1 STI High Drive Input pull-up pull-down pull-up pull-up pull-down pull-down open-drain
Refer toTable 8
SMBus General Purpose I/O System Pins
MSMBCLK MSMBDAT GPIO[9,7,2:0] APWRDISN CCLKDS CCLKUS PERSTN RSTHALT SWMODE[2:0] WAKEN
EJTAG / JTAG
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
LVTTL
STI STI STI STI
pull-up pull-up pull-up pull-up
1. Schmitt Trigger Input (STI).
Table 7 Pin Characteristics
6 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
Logic Diagram -- PES3T3
Reference Clock
PEREFCLKP PEREFCLKN PE0TP[0] PE0TN[0]
PCI Express Switch SerDes Input Port 0
PCI Express Switch SerDes Output Port 0
PE0RP[0] PE0RN[0] PE2TP[0] PE2TN[0]
PCI Express Switch SerDes Input Port 2
PCI Express Switch SerDes Output Port 2
PE2RP[0] PE2RN[0] PE3TP[0] PE3TN[0]
PCI Express Switch SerDes Input Port 3
PE3RP[0] PE3RN[0]
PES3T3
5
PCI Express Switch SerDes Output Port 3
GPIO[9,7,2:0]
General Purpose I/O
MSMBDAT
JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N VDDCORE
3
JTAG Pins
System Pins
CCLKDS CCLKUS RSTHALT PERSTN SWMODE[2:0]
WAKEN APWRDISN
VDDI/O VDDPE VDDAPE VSS VTTPE
Power/Ground
Figure 3 PES3T3 Logic Diagram
7 of 23
September 7, 2007
Advance Information
Master SMBus Interface
MSMBCLK
JTAG_TCK
IDT 89HPES3T3 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13.
Parameter PEREFCLK RefclkFREQ RefclkDC1 TR, TF VSW Tjitter
1. ClkIn 2. 3.
Description
Min
Typical
Max
Unit
Input reference clock frequency range Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing3 Input clock jitter (cycle-to-cycle)
100 40 0.6 50 60 0.2*RCUI 1.6 125
MHz % RCUI2 V ps
Table 8 Input Clock Requirements
must be AC coupled. Use 0.01 -- 0.1 F ceramic capacitors. RCUI (Reference Clock Unit Interval) refers to the reference clock period. AC coupling required.
AC Timing Characteristics
Parameter PCIe Transmit TTX-RISE, TTX-FALL UI TTX-MAX-JITTER TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER
Description
Min
Typical
Max 1101
Units
Rise / Fall time of TxP, TxN outputs Unit Interval Transmitter Total Jitter (peak-to-peak) Minimum Tx Eye Width (1 - TTX-MAX-JITTER) Maximum time between the jitter median and maximum deviation from the median Transmitter data latency (for n=10) Transmitter data latency (for n=20) Transmitter data skew between any 2 lanes Maximum time to transition to a valid electrical idle after sending an Electrical Idle ordered set Time to exit Electrical Idle (L0s) state into L0 Time from asserting Beacon TxEn to beacon being transmitted on the lane Pulse width of RxDetectEn input RxDetectEn falling edge to RxDetect delay Recover data latency for n=10 Recover data latency for n=20 Receiver data skew between any 2 lanes
80 399.88 0.75 400
ps ps UI UI UI bits bits ps ns ns ns ns ns bits bits ns
400.12 0.252 0.15
LTLAT-10 LTLAT-20 TTX-SKEW TTX-IDLE-SET-TOIDLE
9 9 500 4 12 30 9.8 10 1 28 49
11 11 1300 6 16 80 10.2 2 29 60 20
TEIExit TBTEn TRxDetectEn TRxDetect PCIe Receive LRLAT-10 LRLAT-20 TRX-SKEW
Table 9 PCIe AC Timing Characteristics (Part 1 of 2)
8 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet Parameter TBDDly TRX-IDLE_ENTER TRX-IDLE_EXIT TRX-MAX-JITTER TRX-EYE TRX-EYE-MEDIAN-toMAX JITTER
1.
Description Beacon-Activity on channel to detection of Beacon3 Delay from detection of Electrical Idle condition on the channel to assertion of TxIdleDetect output Delay from detection of L0s to L0 transition to de-assertion of TxIdleDetect output Receiver total jitter tolerance Minimum Receiver Eye Width Maximum time between jitter median and max deviation from median
Min
Typical
Max 200
Units s ns ns UI UI UI
10 5
20 10 0.65
0.35 0.325
Table 9 PCIe AC Timing Characteristics (Part 2 of 2)
As measured between 20% and 80% points. Will depend on package characteristics. Compliance Pattern. This is a function of beacon frequency.
2. Measured using PCI Express 3.
Signal GPIO GPIO[9,7,2:0]1
1.
Symbol
Reference Min Max Unit Edge
Timing Diagram Reference
Tpw_13b2
None
50
--
ns
See Figure 4.
Table 10 GPIO AC Timing Characteristics
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous.
2. The values
for this symbol were determined by calculation, not by testing.
EXTCLK Tdo_13a GPIO (synchronous output) Tpw_13b GPIO (asynchronous input) Tdo_13a
Figure 4 GPIO AC Timing Waveform
9 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
Signal JTAG JTAG_TCK
Symbol
Reference Edge
Min
Max
Unit
Timing Diagram Reference
Tper_16a Thigh_16a, Tlow_16a
none
25.0 10.0
50.0 25.0 -- -- 11.3 11.3 --
ns ns ns ns ns ns ns
See Figure 5.
JTAG_TMS1, JTAG_TDI JTAG_TDO JTAG_TRST_N
1.
Tsu_16b Thld_16b Tdo_16c Tdz_16c2 Tpw_16d2
JTAG_TCK rising JTAG_TCK falling none
2.4 1.0 -- -- 25.0
Table 11 JTAG AC Timing Characteristics
2.
The values for this symbol were determined by calculation, not by testing.
Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 5 JTAG AC Timing Waveform Tdz_16c Tper_16a
10 of 23
September 7, 2007
Advance Information
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
IDT 89HPES3T3 Data Sheet
Recommended Operating Supply Voltages
Symbol VDDCORE VDDI/O VDDPE VDDAPE VTTPE VSS Parameter Internal logic supply I/O supply except for SerDes LVPECL/CML PCI Express Digital Power PCI Express Analog Power PCI Express Serial Data Transmit Termination Voltage Common ground Minimum 0.9 3.135 0.9 0.9 1.425 0 Table 12 PES3T3 Operating Voltages Typical 1.0 3.3 1.0 1.0 1.5 0 Maximum 1.1 3.465 1.1 1.1 1.575 0 Unit V V V V V V
Power-Up/Power-Down Sequence
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the power-up sequence.
Recommended Operating Temperature
Grade Commercial Temperature 0C to +70C Ambient Table 13 PES3T3 Operating Temperatures
11 of 23
September 7, 2007
Advance Information
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES3T3, the power-up sequence must be as follows: 1. VDDI/O -- 3.3V 2. VDDCore, VDDPE, VDDAPE -- 1.0V 3. VTTPE -- 1.5V
IDT 89HPES3T3 Data Sheet
Power Consumption
Parameter IDDI/O Typ. tbd Max. tbd Unit mA Conditions Tambient = 25oC Max. values use the maximum voltages listed in Table 12. Typical values use the typical voltages listed in that table.
IDDCore IDDPE, IDD APE ITTPE Power Dissipation
Normal mode Standby mode1
tbd tbd tbd tbd tbd
tbd -- tbd tbd tbd tbd --
mA mA mA mA mA W W
Normal mode Standby mode
1
tbd tbd
1.
All ports in D1 state.
12 of 23
September 7, 2007
Advance Information
Table 14 PES3T3 Power Consumption
IDT 89HPES3T3 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing.
Min1 Typ1 Max1
I/O Type Serial Link
Parameter PCIe Transmit VTX-DIFFp-p VTX-DE-RATIO VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta
Description
Unit
Conditions
Differential peak-to-peak output voltage De-emphasized differential output voltage DC Common mode voltage RMS AC peak common mode output voltage Abs delta of DC common mode voltage between L0 and idle Abs delta of DC common mode voltage between D+ and DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss Transmitter Common Mode Return loss DC Differential TX impedance Single ended TX Impedance TX Eye Height (De-emphasized bits) TX Eye Height (Transition bits)
800 -3 -0.1 1
1200 -4 3.7 20 100 25 20 600
mV dB V mV mV mV mV mV dB dB
delta
VTX-Idle-DiffP VTX-RCV-Detect RLTX-DIFF RLTX-CM ZTX-DEFF-DC ZOSE Transmitter Eye Diagram Transmitter Eye Diagram PCIe Receive VRX-DIFFp-p VRX-CM-AC RLRX-DIFF RLRX-CM ZRX-DIFF-DC ZRX-COMM-DC
12 6 80 40 505 800 100 50 650 950 120 60
mV mV
Differential input voltage (peak-to-peak) Receiver common-mode voltage for AC coupling Receiver Differential Return Loss Receiver Common Mode Return Loss Differential input impedance (DC) Single-ended input impedance
175
1200 150
mV mV dB dB
15 6 80 40 200k 65 100 50 350k 175 120 60
mV
ZRX-COMM-HIGH- Powered down input common mode impedance (DC) Z-DC VRX-IDLE-DETDIFFp-p
Electrical idle detect threshold
PCIe REFCLK CIN Input Capacitance 1.5 -- pF
Table 15 DC Electrical Characteristics (Part 1 of 2)
13 of 23
September 7, 2007
Advance Information
VTX-CM-DC-line-
IDT 89HPES3T3 Data Sheet I/O Type Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) Input IOL IOH IOL IOH VIL VIH VIL VIH Capacitance Leakage CIN Inputs I/OLEAK W/O Pull-ups/downs I/OLEAK WITH Pull-ups/downs
1.
Parameter
Description
Min1
Typ1
Max1
Unit
Conditions
-- -- -- -- -0.3 2.0 -0.3 2.0 -- -- -- --
2.5 -5.5 12.0 -20.0 -- -- -- -- -- -- -- --
-- -- -- -- 0.8 VDDI/O + 0.5 0.8 VDDI/O + 0.5 8.5 + 10 + 10 + 80
mA mA mA mA V V V V pF
VOL = 0.4v VOH = 1.5V VOL = 0.4v VOH = 1.5V -- -- -- -- -- VDDI/O (max) VDDI/O (max) VDDI/O (max)
A A A
Table 15 DC Electrical Characteristics (Part 2 of 2)
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1.
14 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
Package Pinout -- 144-BGA Signal Pinout for PES3T3
The following table lists the pin numbers and signal names for the PES3T3 device.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 VSS VDDIO APWRDISN VTTPE VTTPE PE0TP00 VDDPE PE0RP00 VDDIO SWMODE_0 SWMODE_1 VSS VDDCORE WAKEN CCLKUS VDDPE VDDPE PE0TN00 VDDPE PE0RN00 CCLKDS SWMODE_2 VSS VSS JTAG_TMS VSS VSS VDDCORE VDDAPE VDDAPE VSS VDDCORE VDDCORE VSS Function Alt Pin C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 Function VDDCORE VSS JTAG_TDO MSMBCLK VDDCORE VSS VSS VSS VDDCORE VSS VSS VSS PERSTN RSTHALT JTAG_TDI MSMBDAT VDDIO VDDCORE VSS VDDCORE VSS VSS VSS VDDCORE VSS GPIO_00 JTAG_TCK VDDIO VDDCORE VSS VDDCORE VSS VDDCORE VSS 1 Alt Pin F9 F10 F11 F12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 Function VDDCORE VDDIO VDDIO GPIO_01 VSS JTAG_TRST_N VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS GPIO_02 PEREFCLKP VDDIO VDDAPE VSS VSS VSS VDDCORE VSS VSS VDDCORE VSS GPIO_07 PEREFCLKN VSS VSS VSS VSS VDDCORE 1 1 Alt Pin J7 J8 J9 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 VSS VDDCORE VSS VSS VDDIO GPIO_09 VSS VDDCORE VDDIO VDDPE VSS VDDPE VSS VDDCORE VDDIO VSS VSS PE2RN00 VSS PE2TP00 VSS PE3TN00 VDDAPE PE3RN00 VTTPE NC VSS NC VDDCORE PE2RP00 VSS PE2TN00 VTTPE VDDCORE 1 Function Alt
Table 16 PES3T3 144-pin Signal Pin-Out (Part 1 of 2)
15 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet Pin M5 M6 Function PE3TP00 VSS Alt Pin M7 M8 Function PE3RP00 VDDAPE Alt Pin M9 M10 NC VSS Function Alt Pin M11 M12 NC VSS Function Alt
Table 16 PES3T3 144-pin Signal Pin-Out (Part 2 of 2)
Alternate Signal Functions
Pin E12 G12 H12 J12 GPIO GPIO_00 GPIO_02 GPIO_07 GPIO_09 Alternate P2RSTN IOEXPINTN0 GPEN P3RSTN
Table 17 PES3T3 Alternate Signal Functions
Power Pins
VDDCore B1 C4 C8 C9 C11 D3 D7 E4 E6 E10 F3 F5 F7 VDDCore F9 G4 G6 G8 G10 H7 H10 J6 J8 K2 K4 K9 L12 Table 18 PES3T3 Power Pins VDDI/O A2 A9 E3 F2 F10 F11 H2 J11 K3 K10 VDDPE A7 B4 B5 B7 K5 K7 VDDAPE C5 C6 H3 L6 M8 VTTPE A4 A5 L8 M4
16 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
Ground Pins
Vss A1 A12 B11 B12 C2 C3 C7 C10 C12 D4 D5 D6 D8 D9 Vss D10 E5 E7 E8 E9 E11 F4 F6 F8 G1 G3 G5 G7 G9 Vss G11 H4 H5 H6 H8 H9 H11 J2 J3 J4 J5 J7 J9 J10 Vss K1 K6 K8 K11 K12 L2 L4 L10 M2 M6 M10 M12
Table 19 PES3T3 Ground Pins
Signals Listed Alphabetically
Signal Name APWRDISN CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_07 GPIO_09 JTAG_TCK JTAG_TDI JTAG_TDO JTAG-TMS JTAG-TRST_N MSMBCLK MSMBDAT I/O Type I I I I/O I/O I/O I/O I/O I I I O I I/O I/O Location A3 B9 B3 E12 F12 G12 H12 J12 F1 E1 D1 C1 G2 D2 E2 SMBus JTAG General Purpose Input/Output Signal Category System
Table 20 89PES3T3 Alphabetical Signal List (Part 1 of 2)
17 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet Signal Name No Connection PE0RN00 PE0RP00 PE0TN00 PE0TP00 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 PEREFCLKN PEREFCLKP PERSTN RSTHALT SWMODE_0 SWMODE_1 SWMODE_2 WAKEN VDDCORE, VDDAPE, VDDI/O, VDDPE, VTTPE VSS I I O O I I O O I I O O I I I I I I I I/O I/O Type Location L9, L11, M9, M11 B8 A8 B6 A6 L1 M1 M3 L3 L7 M7 L5 PCI Express Signal Category
J1 H1 D11 D12 A10 A11 B10 B2 See Table 18 for a listing of power pins. System
See Table 19 for a listing of ground pins. Table 20 89PES3T3 Alphabetical Signal List (Part 2 of 2)
18 of 23
September 7, 2007
Advance Information
M5
IDT 89HPES3T3 Data Sheet
PES3T3 Pinout -- Top View
1 2 3 4 5 6 7 8 9 10 11 12
A B C D E F G H J K L M
1 2 3
X
X
A B C D E F G H J K
X X
4 5 6 7 8
X X 9
10
X X
11
L M
12
VDDCore (Power) VDDI/O (Power)
x
VTTPE (Power) VDDPE (Power) VDDAPE (Power)
Vss (Ground)
X
Signals No Connect
19 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
PES3T3 Package Drawing -- 144-Pin BC144/BCG144
20 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
PES3T3 Package Drawing -- Page Two
21 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
Revision History
August 16, 2007: Initial publication of advanced data sheet. September 7, 2007: Added Power-Up/Power Down Sequence.
22 of 23
September 7, 2007
Advance Information
IDT 89HPES3T3 Data Sheet
Ordering Information
NN Product Family A Operating Voltage AAA Device Family NNAN Product Detail AA Device Revision AA A Legend A = Alpha Character N = Numeric Character
Package Temp Range
Blank BC BCG ZA
Commercial Temperature (0C to +70C Ambient) BC144 144-ball CABGA BCG144 144-ball CABGA, Green ZA revision
3T3
3-lane, 3-port
PES
PCI Express Switch
H 89
1.0V +/- 0.1V Core Voltage Serial Switching Product
Valid Combinations
89HPES3T3ZABC 89HPES3T3ZABCG 144-pin BC144 package, Commercial Temperature 144-pin Green BC144 package, Commercial Temperature
(R)
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208
23 of 23
September 7, 2007
Advance Information

▲Up To Search▲

Price & Availability of 89HPES3T3ZABC

	To Download 89HPES3T3ZABC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .